1. Field of the Invention
This invention relates to a drain extended NMOS semiconductor device which has increased breakdown voltage and requires fewer processing steps for fabrication than do prior art NMOS devices with equivalent breakdown voltages.
2. Brief Description of the Prior Art
In the fabrication of NMOS devices, especially for automotive applications, breakdown voltages of such devices required to be at least 40 volts. The prior art standard process for fabrication of NMOS devices yields breakdown voltages of about 33 volts. Additional processing steps must be added to the standard NMOS fabrication process in order to obtain a breakdown voltage of at least 40 volts.
A standard prior art process for fabrication of NMOS transistors generally involved providing a semiconductor material having an lightly doped p-type well therein. The material was then masked to provide an opening in the central region through which there was provided a tank having a shallow light n-type implant. The device was then masked and a heavy doping n-type was implanted at the surface into the central portion of the previously masked region to form a drain region and in the p-type well spaced from the previously masked region to provide a source region. A further masking and heavy doping p-type then takes place in the p-type well remote from the drain to form a backgate. At some time during the process, a heavy doping p-type is provided in the tank between the source and drain regions to provide a channel stop in standard manner. A gate oxide is then formed over the device surface between the source and drain regions and a polysilicon gate electrode is then formed over the gate oxide, both in standard manner.